A processor whose native register is 4096 bits wide
Sparsr is a custom processor architecture for workloads dominated by sparse binary data — bitmaps, molecular fingerprints, hypervectors, parity-check matrices. Mainstream CPUs are 32- or 64-bit machines whose widest SIMD extension tops out around 512 bits. On Sparsr, 4096 bits is the width of the register file and of the instruction set itself. Develop and test locally for free.
What the architecture actually is
Three properties of the machine, stated without comparison to anything else.
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4096
Bits, natively
Wide registers and wide instructions are the point of the machine, not an extension bolted beside a scalar core. The scalar side is a conventional 32-bit RISC core that drives them.
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1
Register per vector
A 4096-dimensional binary vector is a single operand. No eight-register tiling, no loop, no spill traffic, no cross-lane shuffles to reassemble a result.
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Free
To develop and test
The assembler, the runtime and a full software emulator run on your own machine at no cost. Nothing about developing for Sparsr is gated behind hardware access.
Sparse data stays compressed through the load/store path
Sparsr's wide load and store instructions move sparse rows between compressed memory and the wide register file, running them through a compression codec on the way. Compression is part of the addressing model rather than something a kernel does to itself with general-purpose instructions.
That is the part of Sparsr with no equivalent in a baseline instruction set: what the machine can express, rather than how quickly it runs a loop. It is also the part that decides which workloads fit — the codec suits data that is genuinely sparse but not arbitrarily so.
From your laptop to custom silicon
Three stages, and only the first is available to everyone today.
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1
Write and test locally
Write kernels in Sparsr assembly, C or C++, assemble them with spasm, and run them against a full software emulator on your own machine. Free, offline, and suitable for automated testing in CI.
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2
Validate on FPGA
Run the same kernel against the RTL on FPGA hardware. Sparsr's FPGA target is AWS EC2 F2, which serves as the development and validation vehicle for the design. Hosted access is coming.
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3
Extend the instruction set
Sparsr's instruction set is designed to grow. Where a workload needs a wide primitive that does not exist yet, adding it at 4096 bits is ordinary roadmap work — and on a per-project basis it can go as far as a path to dedicated silicon.
The SDK, in full
Everything below runs on your own machine, today, at no cost.
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spasm — the assembler
A cross-assembler for Sparsr assembly, shipped as a single native binary. Wide registers and wide instructions are first-class in the syntax.
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C and C++ intrinsics
sparsr_intrinsics.h exposes the wide instruction set to C and C++, so a kernel does not have to be written in assembly to reach the 4096-bit registers.
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libsparsr_host.so — the runtime
A host library that loads kernels, moves data, and dispatches to a backend. The backend selection is a runtime concern, so host code does not change when the target does.
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Software emulator
A complete emulator for the Sparsr instruction set, running on your own CPU. It implements the instruction set rather than stubbing it, which is what makes a local test result mean something.
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.NET bindings
A managed wrapper over the host runtime, for host applications written in C# rather than C.
Partner with Sparsr
We work with university labs, institutes and grant consortia on custom instruction set extensions and FPGA co-design, and with commercial teams whose workloads are dominated by wide bitwise operations.
If your kernel is mostly AND, XOR and population counts over long bit vectors, we would like to hear about it — including if the primitive you need is one Sparsr does not have yet.